1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit that uses micro-miniaturized elements, for which are required a high degree of integration and a high speed of operation.
2. Description of Related Art
In a semiconductor memory circuit, each memory cell is connected to corresponding one of digit line pairs and corresponding one of word lines, and each load device and sense amplifier are connected via the digit line pair.
FIG. 1 is a semiconductor memory circuit diagram in a prior art. The conventional semiconductor memory circuit includes a memory cell 1 connected to a word line WL and to a digit line pair D1 and D1, a load circuit 11 and a switching circuit 12 that are connected through the digit line pair D1 and D1 to a sense amplifier circuit 13. Memory cells 1A and 1B are similar to the memory cell 1; load circuits 11A and 11B are also similar to the load circuit 11; switching circuits 12A and 12B are also similar to the switching circuit 12 and digit line pairs D2 and D2, D3 and D3 are also similar to the digit line pair D1 and D1, and so that only one set will be taken up and other sets will be omitted unless otherwise needed in the description that will follow.
First, the memory cell 1 includes a flip-flop composed of resistor elements R.sub.1 and R.sub.2 and N channel type insulated gate field effect transistors (hereinafter referred to "NMOS transistors" in plural case and "NMOS transistor" in singular case) MC3 and MC4 (cell transistors), and a switching means for transmission composed of NMOS transistors MC1 and MC2 connected between the digit line pair D1 and D1, and the word line WL. By selecting the word line WL connected to the gates of NMOS transistors MC1 and MC2 in the memory cell 1 and the digit line pair D1 and D1, cell information can be detected as a potential difference between the digit line pair D1 and D1 by means of the conductance ratio of the cell transistors MC3 and MC4, and P channel type insulated gate field effect transistors (hereinafter referred to "PMOS transistors" in plural case and "PMOS transistor" in singular case) M18 and M19 as load elements in the load circuit 11 that are connected to the digit lines D1 and D1.
The switching circuit 12 includes PMOS transistors M20 and M21 as the switching elements that are connected to the digit line pair D1 and D1 and are supplied with a digit selection signal Y1 to their gates, a PMOS transistor M22 that connects between the digit lines, and an inverter INV which supplies the digit selection signal Y1 to the gate of the PMOS transistor M22 by inverting it. The switching circuit 12 sends out the information in the memory cell 1 to the data buses DB and DB via the switching PMOS transistors M20 and M21 that are turned on by the digit selection signal Y1. Information from a plurality of switching circuits 12, 12A and 12B is transmitted to the data buses DB and DB by means of a multiplexer operation, and then transferred to the sense amplifier circuit 13.
Moreover, the sense amplifier circuit 13 includes the input bipolar transistors Q18 and Q19, the differential amplifier bipolar transistors Q20 and Q21, the load resistor elements R9 and R10 and NMOS transistors M23 to M25 that form a constant current source for input emitter-followers and ECL current switches. In particular, the sense amplifier circuit 13 supplies a potential difference information detected between the digit lines D1 and D1 as a difference potential (SB, SB) to the bases of the emitter-coupled bipolar transistors Q20 and Q21 that form a differential amplifier via the input bipolar transistors Q18 and Q19 of the emitter-followers, and output it from S and S by amplifying it to a difference potential sufficient to operate an output buffer (not shown) by means of the load impedance elements R9 and R10 connected to the collectors of the bipolar transistors Q20 and Q21.
Here, the levels in which the digit lines D1 and D1 are in a non-selected state go to potentials which are substantially equal with each other by means of the PMOS transistor M22 for digit line equalization whose gate receives the signal obtained by inverting a digit selection signal Y1 of the switching circuit 12 using the inverter INV, and the digit lines D1 and D1 are in a standby state in order to read the information of the memory cell 1 at high speed in a selected state.
In addition, at the time of writing, by lowering the potential of either of the digit line pair D1 and D1 to a potential below the threshold voltage of the flip-flop for internal level inversion in the memory cell 1, one of the NMOS transistors MC3 and MC4 that is energized of the flip-flop can be turned off and the internal state of the memory cell 1 can be inverted, so that it becomes possible to carry out writing to the memory cell 1.
In short, in the prior art semiconductor memory circuit described in the above, information within the memory cell is detected as the difference between the left and right digit line potentials determined by the conductance ratio of the load PMOS transistors M18, M19 connected respectively to the digit lines D1, D1 that form a pair of left and right lines and the NMOS transistors MC1 to MC4 of the selected memory cell, and the information thus detected is input to the sense amplifier 13 via the switching PMOS transistors M20, M21.
The conventional semiconductor memory circuit described above reads the cell information as the difference between the digit line potentials that are determined by the conductance ratio of the load MOS transistors connected to the memory cell via a digit line pair and the MOS transistors within the memory cell, and leads the information to a sense amplifier. The difference between the source-drain voltages of the load MOS transistors generated by the difference between the currents that flow into the cell (cell current) from either of the left or right digit line of the memory cell, is set to be the digit line potential difference.
Now, a high-speed reading operation requires a high-speed driving of the digit lines. However, the capacitance of the diffused region of the source of a memory cell MOS transistors that is used in large number for parallel connection has a magnitude of about several tens of picofarads. Consequently, MOS transistors with high driving capability are required in order to perform high-speed charging or discharging. It should be noted further that what lifts the digit line potential to a high level is a load MOS transistor while what lowers it is a MOS transistor in the cell.
Therefore, there are disadvantages that when the transistor driving capability is raised, the potential difference between the digit lines becomes small in the former while the cell current is increased in the latter.
Because of this fact, in order to realize a circuit for high-speed reading one has to design the circuit constants so as to have a minimum digit line amplitude that permits the operation of a sense amplifier for an allowable maximum cell current.
In addition, in a semiconductor memory circuit which employs microdevices for which is required a high speed operation, when there is generated a manufacturing error to cause an unbalance in the characteristics of the left and the right MOS transistors within a cell (unbalance between MC1 and MC2, and/or unbalance between MC3 and MC4), load MOS transistors (unbalance between M18 and M19) and switching MOS transistors (unbalance between M20 and M21), there are generated deviations in the high levels and the low levels of the currents that flow in the left and the right data buses connected to the sense amplifier 13. Consequently, the minimum potential difference for detecting the information is reduced.
The nonuniformity in the device properties which has its origin in the fabrication of the devices is observed more frequently in MOS transistors. For example, in a device with gate length of L=1.0 .mu.m, it is inevitable in the manufacturing process to generate an error of about .+-.0.1 .mu.m. By interacting the error with other nonuniformity in characteristics, the sense amplifier input potential difference reduces to about 100 mV to 60 mV, so that it becomes necessary to design a circuit with a preset margin. When a margin is taken for each element, there arises another disadvantage that the operating speed is reduced for a circuit memory as a whole.
Moreover, even in a circuit for which an operating margin is secured, when there are generated unbalances in the device characteristics, the reading speed to have a nonuniformity depending upon the memory cell selected, which leads to a reduction in the access speed for a memory circuit as a whole. Further, this also becomes a cause for an increase in the nonuniformity of the characteristics of the products, and gives rise also to a drawback which causes a reduction in the yield.